Power efficient designs of CNTFET-based ternary SRAM

This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two the proposed are cycle-operator based and third design is buffer-based. The cycle operators buffer used in consume low power as they use two supplies for operation. Ternary logic implementation CNTFETs largely being lately due to advantages it provides terms reduced interconnect complexity chip area. compared with existing HSPICE simulations that a standard Stanford CNTFET model. All show considerable improvement consumption read write operations than their counterparts literature. read, delays noise margins also analysed found be comparable designs.